Noise resistant small signal sensing circuit for a memory device

ABSTRACT

Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input terminals and output terminals of an integrator circuit from a first configuration to a second configuration, where the second configuration changes the polarity of the integrator circuit from the first configuration. The output signals of the integrator circuit are periodically compared, and based on the comparison, output signals having a voltage representative of a value are generated. The values of the output signals are then averaged over time to determine the data state.

TECHNICAL FIELD

[0001] The present invention relates generally to integrated circuitmemory devices, and more specifically, to sensing circuitry for sensingsmall resistance differences in memory cells, such as in resistivememory cells.

BACKGROUND OF THE INVENTION

[0002] Computer systems, video games, electronic appliances, digitalcameras, and myriad other electronic devices include memory for storingdata related to the use and operation of the device. A variety ofdifferent memory types are utilized in these devices, such as read onlymemory (ROM), dynamic random access memory (DRAM), static random accessmemory (SRAM), flash memory (FLASH), and mass storage such as hard disksand CD-ROM or CD-RW drives. Each memory type has characteristics thatbetter suit that type to particular applications. For example, DRAM isslower than SRAM but is nonetheless utilized as system memory in mostcomputer systems because DRAM is inexpensive and provides high densitystorage, thus allowing large amounts of data to be stored relativelycheaply. A memory characteristic that often times determines whether agiven type of memory is suitable for a given application is the volatilenature of the storage. Both DRAM and SRAM are volatile forms of datastorage, which means the memories require power to retain the storeddata. In contrast, mass storage devices such as hard disks and CD drivesare nonvolatile storage devices, meaning the devices retain data evenwhen power is removed.

[0003] Current mass storage devices are relatively inexpensive and highdensity, providing reliable long term data storage at relatively cheap.Such mass storage devices are, however, physically large and containnumerous moving parts, which reduces the reliability of the devices.Moreover, existing mass storage devices are relatively slow, which slowsthe operation of the computer system or other electronic devicecontaining the mass storage device. As a result, other technologies arebeing developed to provide long term nonvolatile data storage, and,ideally, such technologies would also be fast and cheap enough for usein system memory as well. The use of FLASH, which provides nonvolatilestorage, is increasing in popularity in many electronic devices such asdigital cameras. While FLASH provides nonvolatile storage, FLASH is tooslow for use as system memory and the use of FLASH for mass storage isimpractical, due in part to the duration for which the FLASH canreliably store data as well as limits on the number of times data can bewritten to and read from FLASH.

[0004] Due to the nature of existing memory technologies, newtechnologies are being developed to provide high density, high speed,long term nonvolatile data storage. One such technology that offerspromise for both long term mass storage and system memory applicationsis Magneto-Resistive or Magnetic Random Access Memory (MRAM). FIG. 1 isa functional diagram showing a portion of a conventional MRAM array 100including a plurality of memory cells 102 arranged in rows and columns.Each memory cell 102 is illustrated functionally as a resistor since thememory cell has either a first or a second resistance depending on amagnetic dipole orientation of the cell, as will be explained in moredetail below. Each memory cell 102 in a respective row is coupled to acorresponding word line WL, and each memory cell in a respective columnis coupled to a corresponding bit line BL. In FIG. 1, the word lines aredesignated WL1-3 and the bit lines designated BL1-4, and may hereafterbe referred to using either these specific designations or generally asword lines WL and bit lines BL. Each of the memory cells 102 storesinformation magnetically in the form of an orientation of a magneticdipole of a material forming the memory cell, with a first orientationof the magnetic dipole corresponding to a logic “1” and a secondorientation of the magnetic dipole corresponding to a logic “0.” Theorientation of the magnetic dipole of each memory cell 102, in turn,determines a resistance of the cell. Accordingly, each memory cell 102has a first resistance when the magnetic dipole has the firstorientation and a second resistance when the magnetic dipole has thesecond orientation. By sensing the resistance of each memory cell 102,the orientation of the magnetic dipole and thereby the logic state ofthe data stored in the memory cell 102 can be determined.

[0005] The stored logic state can be detected by measuring the memorycell resistance using Ohm's law. For example, resistance is determinedby holding voltage constant across a resistor and measuring, directly orindirectly, the current that flows through the resistor. Note that, forMRAM sensing purposes, the absolute magnitude of resistance need not beknown, the inquiry is whether the resistance is greater or less than avalue that is intermediate to the logic high and logic low states.Sensing the logic state of an MRAM memory element is difficult becausethe technology of the MRAM device imposes multiple constraints. In atypical MRAM device, an element in a high resistance state has aresistance of about 950 kΩ. The differential resistance between a logic“1” and a logic “0” is thus about 50 kΩ, or approximately 5% of scale.

[0006] Therefore, there is a need for a sensing circuit for a resistancemeasuring circuit to repeatably and rapidly distinguish resistancevalues for devices having small signal differentials.

SUMMARY OF THE INVENTION

[0007] The present invention is directed to an apparatus and method fordata sensing that uses averaging to sense small differences in signallevels representing data states. The apparatus includes an integratorcircuit having a first integrator input electrically coupled to areference level, a second integrator input to which an input is applied,and first and second integrator outputs at which first and second outputsignals are provided, respectively. The integrator circuit furtherincludes an amplifier circuit having pairs of differential input andoutput nodes. The integrator circuit periodically switches theelectrical coupling of each of the differential input nodes to arespective integrator input and the electrical coupling of each of thedifferential output nodes to a respective integrator output. Theapparatus further includes a comparator having first and second inputnodes electrically coupled to a respective integrator output and furtherhaving an output node. The clocked comparator periodically comparesvoltage levels of the first and second input nodes and generating anoutput signal having a logic state based therefrom. A current sourcehaving first and second current output nodes coupled to a respectiveintegrator output is also included in the apparatus. The current sourceswitching the coupling of each current output node to a integratoroutput based on the logic state of the output signal of the comparator.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 is a functional block diagram showing a portion of aconventional MRAM array.

[0009]FIG. 2 is a functional block diagram of a sensing circuitaccording to an embodiment of the present invention.

[0010]FIG. 3 is a schematic drawing of an integrator stage according toan embodiment of the present invention.

[0011]FIG. 4 is a schematic drawing of a switching current sourceaccording to an embodiment of the present invention.

[0012]FIG. 5 is a schematic drawing of clocked comparator according toan embodiment of the present invention.

[0013]FIG. 6 is a functional block diagram of a sensing circuitaccording to another embodiment of the present invention.

[0014]FIG. 7 is a functional block diagram illustrating an MRAMincluding a sensing circuit according to the present invention.

[0015]FIG. 8 is a functional block diagram illustrating a computersystem including the MRAM of FIG. 5.

DETAILED DESCRIPTION OF THE INVENTION

[0016] Embodiments of the present invention are directed to a noiseresistant sensing circuit for data sensing circuitry that uses averagingto sense small differences in signal levels representing data states,such as in resistor-based memory circuits. Certain details are set forthbelow to provide a sufficient understanding of the invention. However,it will be clear to one skilled in the art that the invention may bepracticed without these particular details. In other instances,well-known circuits, control signals, and timing protocols have not beenshown in detail in order to avoid unnecessarily obscuring the invention.

[0017]FIG. 2 illustrates an embodiment of a sensing circuit 200according to an embodiment of the present invention. The sensing circuit200 includes an integrator stage 210, a switching current source 212,and a clocked comparator 214. As will be explained in more detail below,an output signal UP (or DOWN) of the sensing circuit 200 is averagedover a period of time to determine the data state stored on a memorycell, such as a resistive memory cell 220. The average value calculatedis indicative of the data state of the memory cell. In summary, thesensing circuit 200 outputs a stream of bits resulting from the cyclicalcharging and discharging of capacitors 340, 342. The ratio of logic “I”bits (or alternatively, logic “0” bits) to a total number of bits yieldsa numerical value that corresponds to an average current through amemory cell, such as resistive memory cell 220, in response to anapplied voltage. The average current, in turn, is used to determine thelogic state of the data stored by the resistive memory cell 220.Circuitry for performing the averaging operation of the bit streamprovided by the sensing circuit 200 has not been shown or described ingreat detail in order to avoid obscuring description of the presentinvention. A more detailed explanation of using current averaging formemory cell sensing is provided in the commonly assigned, co-pendingU.S. patent application Ser. No. 09/938,617, filed Aug. 27, 2001,entitled RESISTIVE MEMORY ELEMENT SENSING USING AVERAGING, which isincorporated herein by reference.

[0018] A potential issue, however, with the circuit described in theaforementioned patent application is related to offset voltages andcurrents inherent with the differential amplifier of the sensingcircuit, as well as 1/ƒnoise. It will be appreciated that these effectscan cause currents in the tens of nano-amperes to be output by thedifferential amplifier. In light of the small voltage margin between twodata states of a memory cell, such as a resistive memory cell, and theresulting magnitude of output current (˜100 nA range) by thedifferential amplifier when reading the memory cell, inherent offsetvoltages and currents, as well as 1/ƒ noise can cause reading errors ifnot compensated. In the sensing circuit described in the aforementionedpatent, offset issues are compensated for by calibrating thedifferential amplifier. However, it is often the case that thecalibration must be adjusted for process variations in fabrication ofthe memory device. Additionally, the process of calibrating thedifferential amplifiers of a memory device is time consuming. As will beexplained in more detail below, embodiments of the present invention,including the arrangement illustrated in FIG. 2, provide offset and 1/ƒnoise compensation without the need for calibration, and allows for theintegration to run indefinitely.

[0019] The operation of the sensing circuit 200 will be describedgenerally with respect to FIG. 2. The resistance Rcell of the resistivememory cell 220 is measured as an input voltage relative to ground. Inreading a memory cell, a wordline (WL) 224 corresponding to a rowaddress is activated and goes HIGH, and bit lines of a memory array arecoupled to the input nodes 226 of the respective sensing circuits 200.All other wordlines in the memory array are grounded. As illustrated inFIG. 2, the voltage level of the selected WL 224 is dropped over Rcelland a “sneak” resistance 222 that represents the resistance of the otherresistive memory cells of the bit line coupled to the input node 226,but not coupled to the selected WL 224. Note that the ground nodecoupled to the sneak resistance 222 represents the unselected, that is,grounded, wordlines.

[0020] For the present example, operation of first and second choppingor switching circuits 230, 234 will be ignored until later in order tosimplify the explanation of the sensing circuit 200. The voltage appliedto the input node 226 causes a differential amplifier 232 to supplycurrent to either node 236 or 238, and draw current from the other node.As a result, the capacitor coupled to the node to which the differentialamplifier 232 is supplying a current will be charged, increasing thevoltage of the node. Conversely, the capacitor coupled to the node fromwhich the differential amplifier 232 is drawing current will bedischarged, decreasing the voltage of that node. A clocked comparator250 senses the relative voltages of the nodes 236, 238 in response to aclock signal Comp_clk and generates a corresponding output signal UP.The clocked comparator 250 also generates a complementary output signalDOWN. As illustrated in FIG. 2, an inverter 252 is coupled to the outputof the clocked comparator 250 to generate the DOWN signal. However, itwill be appreciated that the clocked comparator 250 is provided by wayof example, and a clocked comparator suitable for use with the presentinvention can be implemented in many different ways other than thatshown in FIG. 2.

[0021] The UP and DOWN signals are provided to the switching currentsource 212 having a first current source 260 and a second current source261. Each of the current sources 260, 261 switch between being coupledto the nodes 236, 238 based on the state of the UP and DOWN signals. Inone state, the current source 260 is coupled to the node 236, providingcurrent to positively charge the capacitor 236, and the current source261 is coupled to the node 238, providing current to negatively chargethe capacitor 238. In the other state, the current source 260 is coupledto the node 238, providing current to positively charge the capacitor238, and the current source 261 is coupled to the node 236, providingcurrent to negatively charge the capacitor 236. Consequently, where theUP and DOWN signals switch states, the coupling of the current sources260, 261 will switch as well.

[0022] For example, as illustrated in FIG. 2, the UP and DOWN signalsare LOW and HIGH, respectively, causing the current source 260 to becoupled to the node 236 and the current source to be coupled to the node238. Upon the next rising edge of the Comp_clk signal, the voltages ofthe nodes 236, 238 are sensed by the clocked comparator 250. Thevoltages at the nodes 236, 238 are represented by signals intout1p andintout1m, respectively. Where the coupling of the current sources 260,261 are such that the current provided to the capacitors 240, 242 overthe period of the Comp_clk signal causes the voltages of the nodes 236,238 to change from the previous rising edge of the Comp_clk signal, theoutput of the clocked comparator 250 changes logic states. This in turncauses the coupling of the current sources 260, 261 to switch nodes aswell. It will be appreciated that the coupling of the current sources260, 261 will continue to switch until the current provided by thedifferential amplifier 232 to either one of the capacitors 240, 242causes the voltage of the respective node 236, 238 to be greater thanthe change in voltage caused by the current source over one period ofthe Comp_clk signal. When this occurs, the logic states of the UP andDOWN signals maintain their present logic states, which causes theaverage of the output signal of the sensing circuit 200 to change.

[0023] As previously mentioned, operation of the first and secondswitching circuits 230, 234 has been ignored. Operation of the first andsecond switching circuits 230, 234 will now be discussed. Explainedbriefly, the first and second switching circuits 230, 234 are used tozero out any inherent offset with the differential amplifier 232 and 1/ƒnoise. As previously discussed, offset voltages and currents, as well as1/ƒ noise cause reading errors if not compensated. As will be explainedin more detail below, in embodiments of the present invention, offsetand 1/ƒ noise compensation can be provided without the need forcalibration, and additionally, integration can be run indefinitely.

[0024]FIG. 3 illustrates an embodiment of an integrator stage 300 thatcan be substituted for the integrator stage 210 in FIG. 2. Theintegrator stage 300 includes an input multiplexer 320 coupled to afirst switching circuit 14 at an input node 322. The multiplexer 320selects between coupling a first digit line signal SA_in_(—)0 and asecond digit line signal SA_in_(—)1 to the input node 322 based on thelogic states of address signals B0 and B1. The address signals B0 and B1are conventional, and provision of these types of signals to theintegrator stage 300 are well known in the art. A second input node 324of the first switching circuit 314 is coupled to ground through atransistor 328. The gate of the transistor 328 is coupled to a powersupply making the transistor 328 conductive. Output nodes 332, 334 arecoupled to non-inverting and inverting inputs of the differentialamplifier 310, respectively. Non-inverting and inverting outputs of thedifferential amplifier 310 are coupled to input nodes 336, 338,respectively, of the second switching circuit 318. Output nodes 346, 348of the second switching circuit 318 are coupled to capacitors 340, 342,respectively. As previously discussed, the intout1p and intout1m signalsprovided by the integrator stage 210 (FIG. 2) to the clocked comparator214 represent the voltages at the nodes 330, 332 as the capacitors 340,342 charge and discharge. The integrator stage 300 further includes acommon-mode feedback circuit 352 coupled to the output nodes 346, 348 ofthe second switching circuit 318 to limit the output current of thedifferential amplifier 310 to a differential current. The voltages,Vbias1, Vbias2, Vbias3, and Vbias4, illustrated in FIG. 3 are biasvoltages that can be generated and provided to the integrator stage 300in any conventional manner. It will be appreciated that selection of thespecific voltage levels can be made by those of ordinary skill in theart based on the description of the present invention provided herein.

[0025] Operation of the integrator stage 300 is essentially the same aspreviously explained with respect to FIG. 2. However, operation of theintegrator stage 300 is modified by the operation of the first andsecond switching circuits 314, 318. The first and second switchingcircuits 314, 318 receive complementary clock signals switchclk andswitchclk*. The switchclk and switchclk* signals can be generated in anyconventional manner, and typically have a lower frequency than theComp_clk signal provided to the clocked comparator 214 (FIG. 2). Theswitching circuits 314, 318 generally switch the coupling of the inputnodes to the output nodes back-and-forth in synchronicity with theswitchclk signal. As will be explained in more detail below, byperiodically switching the coupling of the input and output nodes of theswitching circuits 314, 318, and then making a determination of the datavalue stored in a memory cell by averaging multiple samples, any offsetissues with the integrator circuit 310 and 1/ƒ noise can be averagedout.

[0026] For example, assume that the differential amplifier 310 has anoffset that causes a first offset current to flow out of differentialamplifier at the node 336 (i.e., positive polarity) and a second offsetcurrent to flow into the differential amplifier at the node 338 (i.e.,negative polarity). When the switchclk signal transitions HIGH, NMOStransistors 360, 361 of the first switching circuit 314 becomeconductive, coupling the input node 322 to the output node 332, andcoupling the input node 324 to the output node 334. As for the secondswitching circuit 318, PMOS transistors 364, 365 become conductive,coupling the input node 336 to the output node 346, and coupling theinput node 338 to the output node 348. Thus, during the time theswitchclk signal is HIGH, the positive polarity of the first offsetcurrent adds to the output current applied to the capacitor 340 and thenegative polarity of the second offset current subtracts from the outputcurrent applied to the capacitor 342.

[0027] When the switchclk signal transitions LOW, however, the couplingof the input and output nodes of the first and second switching circuits314, 318 switch. That is, when the switchclk signal is LOW, NMOStransistors 362, 363 of the first switching circuit 314 becomeconductive (and NMOS transistors 360, 361 switch OFF), switching thecoupling of the input node 322 to the output node 334 and the couplingoff the input node 324 to the output node 332. Similarly, in the secondswitching circuit 318, PMOS transistors 366, 367 become conductive (andPMOS transistors 364, 365 switch OFF) switching the coupling of theinput node 336 to the output node 348, and the coupling of the inputnode 338 to the output node 346. In this arrangement, the first offsetcurrent now adds to the output current applied to the capacitor 342 andthe second offset current now subtracts from the output current appliedto the capacitor 340.

[0028] As a result of the switching of the input and output nodes of theswitching circuits 314 and 318, the positive and negative offsetcurrents are applied to each of the capacitors for an equal time. Thus,where the data state of a memory cell is based on the average ofmultiple samples taken over a period of time (preferably a multiple ofthe switchclk signal), the offset currents inherent with thedifferential amplifier 310 can be averaged out.

[0029]FIG. 4 illustrates an embodiment of a current source 400 that canbe substituted for the current sources 260, 261 illustrated in FIG. 2.The current source includes PMOS transistors 420, 422 that couple apower supply having a voltage of Vdd to a node 426, and NMOS transistors430, 432 that couple a node 436 to ground. Each of the PMOS and NMOStransistors 420, 422, 430, and 432 have a respective voltage applied totheir gates to set the conductivity. As previously discussed, thevoltages, Vbias1, Vbias2, Vbias3, and Vbias4, are selected to set themagnitude of current supplied to the nodes 426 and 436. These voltagescan be generated and provided to the current source 400 in anyconventional manner.

[0030] The current source 400 further includes PMOS switchingtransistors 404 a, 404 b and NMOS switching transistors 408 a, 408 b.The Down_int and Up_int signals are applied to the gates of thetransistors 404 a, 408 a and 404 b, 408 b, respectively. The switchingtransistors 404 a, 408 a, 404 b, 408 b, alternatively couple nodes 410a, 410 b to either the power supply or ground, depending on the logicstates of the Down_int and Up_int signals. As previously discussed, theDown_int and Up_int signals have complementary logic states, and aregenerated as output signals of the clocked comparator 214 (FIG. 2). Thenodes 410 a, 410 b represent the nodes to which the capacitors of theintegrator stage 210 (FIG. 2) are coupled. Thus, because of theircomplementary logic states, the nodes 410 a, 410 b are alternativelycharged or discharged based on the switching of the Down_int and Up_intsignals.

[0031] In operation, when the Up_int signal is HIGH (and the Down_intsignal is LOW), current is being supplied to the node 410 a and drawnfrom the node 410 b. When the Up_int and Down_int signals switch to LOWand HIGH, respectively, current is then drawn from the node 410 a andsupplied to the node 410 b. As the Up_int and Down_int signals continueto switch logic states, the current supplied or sunk alternates betweenthe nodes 410 a, 410 b as well.

[0032]FIG. 5 illustrates an embodiment of a clocked comparator 500 thatcan be substituted for the clocked comparator 214 illustrated in FIG. 2.The clocked comparator 500 includes a latch circuit 502 formed fromcross-coupled PMOS transistors 504, 506 and cross-coupled NMOStransistors 508, 510. A first logic state and a complementary secondlogic state are latched at nodes 514 and 516, respectively. Coupled tothe nodes 514 and 516 is an active-low set-reset (SR) flip-flop 520having two output nodes at which Up_int and Down_int signals areprovided. The Up_int and Down_int signals are provided to an averagingcircuit (not shown) for determination of the data state of a memorycell. The active-low SR flip-flop 520 is conventional in design andoperation. That is, where the logic state at the node 516 switches toLOW, the Up_int signal will be HIGH, and where the logic state at thenode 514 switches to LOW, the Down_int signal will be HIGH. Where thelogic state at both the nodes 514 and 516 are HIGH, the Up_int andDown_int signals will remain the same.

[0033] PMOS transistors 550 a, 550 b are coupled in parallel to the PMOStransistors 504 and 506, respectively. NMOS transistors 554 a, 554 b arecoupled between the cross-coupled PMOS transistors 504 and 506 and thecross-coupled NMOS transistors 508 and 510. A Comp_clk clock signal isapplied to the gates of PMOS transistors 550 a, 550 b and the NMOStransistors 554 a, 554 b. The Comp_clk signal can be produced in anyconventional manner. The clocked comparator 500 further includes NMOStransistors 560 a, 560 b coupled in parallel to the NMOS transistors 508and 510, respectively. The intout1p and intout1m signals are applied tothe gates of the NMOS transistors 508 and 510, respectively.

[0034] In operation, the clocked comparator 500 provides Up_int andDown_int signals in synchronicity with the Comp_clk signal for averagingbased on logic state of the intout1p and intout1m signals of theintegrator stage 210 (FIG. 2). Starting at the rising edge of theComp_clk signal, the clocked comparator 500 sets the logic state of theUp_int and Down_int signals based on the logic state of the intout1p andinout1m signals. Upon the falling edge of the Comp_clk signal, the logicstates of the intout1p and intout1m signals are maintained in theirpresent state until the period of the Comp_clk signal is complete.

[0035] For example, during the time the Comp_clk signal is HIGH, thelatch circuit 502 is “active,” latching logic states at the nodes 514,516 in response to the logic states of the intout1p and intout1msignals. Note, that during the time the Comp_clk signal is HIGH, boththe PMOS transistors 550 a, 550 b are OFF, thus, allowing the nodes 514,516 to be set according to the logic states of the intout1p and intout1msignals. When the latch circuit 502 is active, and the inout1m signal isHIGH, the node 516 is pulled LOW, activating the PMOS transistor 504.This in turn pulls the node 514 HIGH and activates the NMOS transistor510. As a result, the Up_int signal provided at the output of theactive-low SR flip-flop 520 switches or remains HIGH, and the Down_intsignal switches or remains LOW. Upon the Comp_clk signal going LOW, boththe NMOS transistors 554 a, 554 b are switched OFF isolating the nodes514 and 516 from the cross coupled NMOS transistors 508 and 510.Additionally, both the PMOS transistors 550 a, 550 b become conductive,and the nodes 514, 516 are coupled to a power supply having a voltage ofVdd, pulling the nodes 514, 516 HIGH. As previously mentioned, when boththe inputs of the active-low SR flip-flop 520 are HIGH, the logic stateof the Up_int and Down_int signals are maintained in their presentstate.

[0036] When the Comp_clk signal goes HIGH again, and the logic states ofthe intout1m and intout1p signals have switched to LOW and HIGH,respectively, the node 514 will be pulled LOW and the node 516 will bepulled HIGH. As a result, the Up_int and Down_int signals will switch aswell, with the Up_int signal changing from a HIGH logic state to a LOWone, and the Down_int signal changing from a LOW logic state to a HIGHone. For the remainder of the Comp_clk cycle, the logic states of theUp_int and Down_int signals will be maintained in their present state.

[0037] It will be appreciated that the embodiments of the integratorstage 300, the current source 400, and the clocked comparator 500 shownin FIGS. 3-5 and previously discussed, have been provided by way ofexample. The description provided herein is sufficient to enable one ofordinary skill in the art to implement the previously described circuitsand provide the same functionality and operability, but in alternativemanners. It will be further appreciated that modifications such as theseare well within the scope of the present invention.

[0038]FIG. 6 illustrates a sensing circuit 600 according to analternative embodiment of the present invention. The sensing circuit 600includes a first integrator stage 602, a second integrator stage 604, aclocked comparator 606, and first and second switched current sources610, 612. Operation of the sensing circuit 600 is similar to theoperation of the sensing circuit 200 illustrated in FIG. 2. The sensingcircuit 600 is different in that a second integrator stage 604 and asecond switched current source 612 has been included. The secondintegrator stage 604 provides increased gain over the sensing circuit200, as well as second order noise shaping. The integrator stage 200 canbe substituted for the integrator stages 602, 604. However, switchingcircuits, similar to first and second switching circuits 230, 234 (FIG.2) can be omitted from the second integrator stage since the voltagelevels of the output signals from the first integrator stage 602 isgreat enough where inherent offsets in the second integrator stage 604and 1/ƒ noise is less likely to cause reading errors. It will beappreciated that the description provided herein, including thedescription related to the function and operation of the sensing circuit200, is sufficient to enable one of ordinary skill in the art topractice the invention.

[0039]FIG. 7 is a simplified block diagram of a memory device 700including an MRAM array 701 having sense circuitry 710 according to anembodiment of the present invention. The memory device 700 furtherincludes an address decoder 702 that receives addresses from externalcircuitry (not shown), such as a processor or memory controller, on anaddress bus ADDR. In response to the received addresses, the addressdecoder 702 decodes the addresses and applies decoded address signals toaccess corresponding MRAM memory cells in the MRAM array 701. Aread/write circuit 704 transfers data on a data bus DATA to addressedmemory cells in the MRAM array 701 during write operations, andtransfers data from addressed memory cells in the array onto the databus during read operations. A control circuit 706 applies a plurality ofcontrol signals 708 to control the MRAM array 701, address decoder 702and read/write circuit 704 during operation of the MRAM 700.

[0040] In operation, the external circuitry provides address, control,and data signals to the MRAM 700 over the respective ADDR, CONT, andDATA busses. During a write cycle, the external circuitry providesmemory addresses on the ADDR bus, control signals on the CONT bus, anddata on the DATA bus. In response to the control signals, the controlcircuit 706 generates controls signals 708, to control the memory-cellarray 701, address decoder 702, and read/write circuitry 704. Theaddress decoder 702 decodes the memory address on the ADDR bus andprovides decoded address signals to select the corresponding memorycells in the memory-cell array 701. The read/write circuitry 704receives write data on the DATA bus, and applies the write data to thememory-cell array 701 to store the data in the selected memory cells.

[0041] During a read cycle, the external circuitry provides a memoryaddress on the ADDR bus and control signals on the CONT bus. Once again,in response to the control signals, the control circuit 706 generatescontrols signals 708 to control the memory-cell array 701, addressdecoder 702, and read/write circuitry 704. In response to the memoryaddress, the address decoder 702 provides decoded address signals toaccess the corresponding memory cells in the array 701. The read/writecircuitry 704 provides data stored in the addressed memory cells ontothe DATA bus to be read by the external circuit. One skilled in the artwill understand circuitry for forming the address decoder 702,read/write circuitry 704, and control circuit 706, and thus, for thesake of brevity, these components are not described in more detail.Although only a single array 701 is shown in the MRAM 700, the MRAM mayinclude a plurality of arrays, and may also include additionalcomponents not illustrated in FIG. 7.

[0042]FIG. 8 is a block diagram of a computer system 800 includingcomputer circuitry 802 that contains the MRAM 700 of FIG. 7. Thecomputer circuitry 802 performs various computing functions, such asexecuting specific software to perform specific calculations or tasks.In addition, the computer system 800 includes one or more input devices804, such as a keyboard or a mouse, coupled to the computer circuitry802 to allow an operator to interface with the computer system.Typically, the computer system 800 also includes one or more outputdevices 806 coupled to the computer circuitry 802, such output devicestypically being a printer or video display. One or more data storagedevices 808 are also typically coupled to the computer circuitry 802 tostore data or retrieve data from external storage media (not shown).Examples of typical storage devices 808 include hard and floppy disks,tape cassettes, compact disc read-only memories (CDROMs), read-write CDROMS (CD-RW), and digital video discs (DVDs). Moreover, although theMRAM 700 is shown as being part of the computer circuitry 802, the MRAMcan also be used as a data storage device 808 since, as previouslydescribed, the nonvolatile nature and speed of the MRAM make it anattractive alternative to other storage media devices such as harddisks.

[0043] From the foregoing it will be appreciated that, although specificembodiments of the invention have been described herein for purposes ofillustration, various modifications may be made without deviating fromthe spirit and scope of the invention. Accordingly, the invention is notlimited except as by the appended claims.

1. A sensing circuit, comprising: an integrator circuit having a firstintegrator input electrically coupled to a reference level, a secondintegrator input to which an input is applied, and first and secondintegrator outputs at which first and second output signals areprovided, respectively, the integrator circuit further having anamplifier circuit having pairs of differential input and output nodes,the integrator circuit periodically switching the electrical coupling ofeach of the differential input nodes to a respective integrator inputand the electrical coupling of each of the differential output nodes toa respective integrator output; a comparator having first and secondinput nodes electrically coupled to a respective integrator output andfurther having an output node, the clocked comparator periodicallycomparing voltage levels of the first and second input nodes andgenerating an output signal having a logic state based therefrom; and acurrent source having first and second current output nodes coupled to arespective integrator output, the current source switching the couplingof each current output node to a integrator output based on the logicstate of the output signal of the comparator.
 2. The sensing circuit ofclaim 1 wherein the period at which the integrator circuit switches thecoupling of the differential input and output nodes is greater than theperiod at which the comparator compares the voltage levels of the firstand second input nodes.
 3. The sensing circuit of claim 1 wherein thecomparator comprises: a clocked latch having a pair of complementarydata nodes, first and second input terminals coupled to a respectiveintegrator output, the clocked latch latching data states applied to thefirst and second input terminals; and a flip-flop electrically coupledto the complementary data nodes for providing an output signalindicative of the latched data states.
 4. The sensing circuit of claim 3wherein the clocked latch latches the data states at its first andsecond input terminals for a first half of the period at which thecomparator compares voltage levels, and the clocked latch is set to areference voltage level for a second half of the period.
 5. The sensingcircuit of claim 1 wherein the integrator circuit comprises: a firstswitching circuit having a first pair of switches for electricallycoupling the first integrator input to the first differential input andthe second integrator input to the second differential input, and asecond pair of switches for electrically coupling the first integratorinput to the second differential input and the second integrator inputto the first differential input; and a second switching circuit having afirst pair of switches for electrically coupling the first differentialoutput to the first integrator output and the second differential outputto the second integrator output, and a second pair of switches forelectrically coupling the first differential output to the secondintegrator output and the second differential output to the firstintegrator output.
 6. The sensing circuit of claim 5 wherein the firstpairs of switches of the first and second switching circuits areactivated for the first half of the period at which the integratorcircuit switches the coupling, and the second pairs of switches of thefirst and second switching circuits are activated for the second half ofthe period.
 7. The sensing circuit of claim 1, further comprising afeedback stage electrically coupled to the first and second integratoroutputs and the amplifier circuit, the feedback stage adjusting outputcurrent of the amplifier circuit based on the relative voltage levels ofthe first and second integrator outputs.
 8. A sensing circuit having asensing node electrically coupled to a memory cell and reference nodeelectrically coupled to a reference level, the sensing circuitcomprising: a differential amplifier having first and seconddifferential input and output nodes; a switching circuit having firstand second switching input and output terminals, and a clock node atwhich a first clock signal is applied, the switching circuitelectrically coupled to the differential input and output nodes and, inaccordance with the first clock signal, switching the coupling of thefirst and second switching input nodes to a respective differentialinput node and switching the coupling of the first and second switchingoutput nodes to a respective differential output node; first and secondcapacitors electrically coupled to a respective switching output node; aclocked comparator having an output node, a clock node at which a secondclock signal is applied, and first and second input nodes electricallycoupled to a respective capacitor, in response to the second clocksignal, the clocked comparator generating an output signal having alogic state based on the relative voltage levels of the first and secondcapacitors; and a current source having first and second current outputnodes electrically coupled to a respective capacitor, the current sourceswitching the coupling of each current output node to a respectivecapacitor based on the logic state of the output signal of the clockedcomparator.
 9. The sensing circuit of claim 8, further comprising afeedback stage electrically coupled to the first and second capacitorsand the differential amplifier, the feedback stage adjusting outputcurrent of the differential amplifier based on the relative voltagelevels of the first and second capacitors.
 10. The sensing circuit ofclaim 8 wherein the clocked comparator comprises: a clocked latch havinga pair of complementary data nodes, first and second input terminalselectrically coupled to a respective capacitor, and a clock node atwhich the second clock signal is applied; and a flip-flop electricallycoupled to the complementary data nodes for providing an output signalindicative of the data states of the complementary data nodes.
 11. Thesensing circuit of claim 8 wherein the first clock signal has afrequency greater than the second clock signal.
 12. The sensing circuitof claim 8, further comprising an integrator circuit having a pair ofintegrator input nodes and a pair of integrator output nodes, theintegrator circuit electrically interposed between the first and secondcapacitors and the clocked comparator, each integrator input node of thepair electrically coupled to a respective capacitor and each integratoroutput node of the pair electrically coupled to a respective input nodeof the clocked comparator.
 13. A sensing circuit, comprising: a firstintegrator circuit having a first integrator input electrically coupledto a reference level, a second integrator input to which an input isapplied, and first and second integrator outputs at which first andsecond output signals are provided, respectively, the integrator circuitfurther having an amplifier circuit having pairs of differential inputand output nodes, the integrator circuit periodically switching theelectrical coupling of each of the differential input nodes to arespective integrator input and the electrical coupling of each of thedifferential output nodes to a respective integrator output; a secondintegrator circuit having first and second integrator inputs coupled toa respective integrator output of the first integrator circuit and firstand second integrator outputs; a comparator having first and secondinput nodes electrically coupled to a respective integrator output ofthe second integrator circuit and further having an output node, theclocked comparator periodically comparing voltage levels of the firstand second input nodes and generating an output signal having a logicstate based therefrom; and a current source having a first pair ofcurrent output nodes coupled to a respective integrator output of thefirst integrator circuit, and further having a second pair of currentoutput nodes coupled to a respective integrator output of the secondintegrator circuit, the current source switching the coupling of eachcurrent output node of the first pair to a respective integrator outputof the first integrator circuit, and each current output node of thesecond pair to a respective integrator output of the second integratorcircuit based on the logic state of the output signal of the comparator.14. The sensing circuit of claim 13 wherein the period at which thefirst integrator circuit switches the coupling of the differential inputand output nodes is greater than the period at which the comparatorcompares the voltage levels of the first and second input nodes.
 15. Thesensing circuit of claim 13 wherein the comparator comprises: a clockedlatch having a pair of complementary data nodes, first and second inputterminals coupled to a respective integrator output of the secondintegrator, the clocked latch latching data states applied to the firstand second input terminals; and a flip-flop electrically coupled to thecomplementary data nodes for providing an output signal indicative ofthe latched data states.
 16. The sensing circuit of claim 13 wherein theclocked latch latches the data states at its first and second inputterminals for a first half of the period at which the comparatorcompares voltage levels, and the clocked latch is set to a referencevoltage level for a second half of the period.
 17. The sensing circuitof claim 13 wherein the first integrator circuit comprises: a firstswitching circuit having a first pair of switches for electricallycoupling the first integrator input to the first differential input andthe second integrator input to the second differential input, and asecond pair of switches for electrically coupling the first integratorinput to the second differential input and the second integrator inputto the first differential input; and a second switching circuit having afirst pair of switches for electrically coupling the first differentialoutput to the first integrator output and the second differential outputto the second integrator output, and a second pair of switches forelectrically coupling the first differential output to the secondintegrator output and the second differential output to the firstintegrator output.
 18. The sensing circuit of claim 17 wherein the firstpairs of switches of the first and second switching circuits areactivated for the first half of the period at which the integratorcircuit switches the coupling, and the second pairs of switches of thefirst and second switching circuits are activated for the second half ofthe period.
 19. The sensing circuit of claim 13 wherein the firstintegrator circuit further comprising a feedback stage electricallycoupled to the first and second integrator outputs of the firstintegrator and the amplifier circuit, the feedback stage adjustingoutput current of the amplifier circuit based on the relative voltagelevels of the first and second integrator outputs of the firstintegrator circuit.
 20. A memory device, comprising: an address bus; acontrol bus; a data bus; an address decoder coupled to the address bus;a control circuit coupled to the control bus; an MRAM array coupled tothe address decoder and control circuit, the MRAM array having aplurality of word lines, a plurality of bit lines, a plurality of memorycells arranged in rows and columns, each memory cell in a respective rowbeing coupled to a corresponding word line and each memory cell inrespective column being coupled to a corresponding bit line; and; aread/write circuit coupled to the data bus and the MRAM array, theread/write circuit including sensing circuits coupled to the bit lines,each sensing circuit comprising: an integrator circuit having a firstintegrator input electrically coupled to a reference level, a secondintegrator input coupled to a respective bit line, and first and secondintegrator outputs at which first and second output signals areprovided, respectively, the integrator circuit further having anamplifier circuit having pairs of differential input and output nodes,the integrator circuit periodically switching the electrical coupling ofeach of the differential input nodes to a respective integrator inputand the electrical coupling of each of the differential output nodes toa respective integrator output; a comparator having first and secondinput nodes electrically coupled to a respective integrator output andfurther having an output node, the clocked comparator periodicallycomparing voltage levels of the first and second input nodes andgenerating an output signal having a logic state based therefrom; and acurrent source having first and second current output nodes coupled to arespective integrator output, the current source switching the couplingof each current output node to a integrator output based on the logicstate of the output signal of the comparator.
 21. The memory device ofclaim 20 wherein the period at which the integrator circuit in thesensing circuit switches the coupling of the differential input andoutput nodes is greater than the period at which the comparator comparesthe voltage levels of the first and second input nodes.
 22. The memorydevice of claim 20 wherein the comparator of the sensing circuitcomprises: a clocked latch having a pair of complementary data nodes,first and second input terminals coupled to a respective integratoroutput, the clocked latch latching data states applied to the first andsecond input terminals; and a flip-flop electrically coupled to thecomplementary data nodes for providing an output signal indicative ofthe latched data states.
 23. The memory device of claim 22 wherein theclocked latch of the sensing circuit latches the data states at itsfirst and second input terminals for a first half of the period at whichthe comparator compares voltage levels, and the clocked latch is set toa reference voltage level for a second half of the period.
 24. Thememory device of claim 20 wherein the integrator circuit of the sensingcircuit comprises: a first switching circuit having a first pair ofswitches for electrically coupling the first integrator input to thefirst differential input and the second integrator input to the seconddifferential input, and a second pair of switches for electricallycoupling the first integrator input to the second differential input andthe second integrator input to the first differential input; and asecond switching circuit having a first pair of switches forelectrically coupling the first differential output to the firstintegrator output and the second differential output to the secondintegrator output, and a second pair of switches for electricallycoupling the first differential output to the second integrator outputand the second differential output to the first integrator output. 25.The memory device of claim 24 wherein the first pairs of switches of thefirst and second switching circuits are activated for the first half ofthe period at which the integrator circuit switches the coupling, andthe second pairs of switches of the first and second switching circuitsare activated for the second half of the period.
 26. The memory deviceof claim 20 wherein the sensing circuit further comprises a feedbackstage electrically coupled to the first and second integrator outputsand the amplifier circuit, the feedback stage adjusting output currentof the amplifier circuit based on the relative voltage levels of thefirst and second integrator outputs.
 27. The memory device of claim 20wherein the integrator circuit is a first integrator circuit, and thesensing circuit further comprises a second integrator circuit having apair of integrator input nodes and a pair of integrator output nodes,the second integrator circuit electrically interposed between the firstand second integrator outputs of the first integrator circuit and thecomparator, each integrator input node of the pair electrically coupledto a respective integrator output of the first integrator circuit andeach integrator output node of the pair electrically coupled to arespective input node of the comparator.
 28. A computer system,comprising: a data input device; a data output device; a processorcoupled to the data input and output devices; and a memory devicecoupled to the processor, the memory device comprising, an address bus;a control bus; a data bus; an address decoder coupled to the addressbus; a control circuit coupled to the control bus; an MRAM array coupledto the address decoder and control circuit, the MRAM array having aplurality of word lines, a plurality of bit lines, a plurality of memorycells arranged in rows and columns, each memory cell in a respective rowbeing coupled to a corresponding word line and each memory cell inrespective column being coupled to a corresponding bit line; and; aread/write circuit coupled to the data bus and the MRAM array, theread/write circuit including sensing circuits coupled to the bit lines,each sensing circuit comprising: an integrator circuit having a firstintegrator input electrically coupled to a reference level, a secondintegrator input coupled to a respective bit line, and first and secondintegrator outputs at which first and second output signals areprovided, respectively, the integrator circuit further having anamplifier circuit having pairs of differential input and output nodes,the integrator circuit periodically switching the electrical coupling ofeach of the differential input nodes to a respective integrator inputand the electrical coupling of each of the differential output nodes toa respective integrator output; a comparator having first and secondinput nodes electrically coupled to a respective integrator output andfurther having an output node, the clocked comparator periodicallycomparing voltage levels of the first and second input nodes andgenerating an output signal having a logic state based therefrom; and acurrent source having first and second current output nodes coupled to arespective integrator output, the current source switching the couplingof each current output node to a integrator output based on the logicstate of the output signal of the comparator.
 29. The computer system ofclaim 28 wherein the period at which the integrator circuit in thesensing circuit switches the coupling of the differential input andoutput nodes is greater than the period at which the comparator comparesthe voltage levels of the first and second input nodes.
 30. The computersystem of claim 28 wherein the comparator of the sensing circuitcomprises: a clocked latch having a pair of complementary data nodes,first and second input terminals coupled to a respective integratoroutput, the clocked latch latching data states applied to the first andsecond input terminals; and a flip-flop electrically coupled to thecomplementary data nodes for providing an output signal indicative ofthe latched data states.
 31. The computer system of claim 30 wherein theclocked latch of the sensing circuit latches the data states at itsfirst and second input terminals for a first half of the period at whichthe comparator compares voltage levels, and the clocked latch is set toa reference voltage level for a second half of the period.
 32. Thecomputer system of claim 28 wherein the integrator circuit of thesensing circuit comprises: a first switching circuit having a first pairof switches for electrically coupling the first integrator input to thefirst differential input and the second integrator input to the seconddifferential input, and a second pair of switches for electricallycoupling the first integrator input to the second differential input andthe second integrator input to the first differential input; and asecond switching circuit having a first pair of switches forelectrically coupling the first differential output to the firstintegrator output and the second differential output to the secondintegrator output, and a second pair of switches for electricallycoupling the first differential output to the second integrator outputand the second differential output to the first integrator output. 33.The computer system of claim 32 wherein the first pairs of switches ofthe first and second switching circuits are activated for the first halfof the period at which the integrator circuit switches the coupling, andthe second pairs of switches of the first and second switching circuitsare activated for the second half of the period.
 34. The computer systemof claim 28 wherein the sensing circuit further comprises a feedbackstage electrically coupled to the first and second integrator outputsand the amplifier circuit, the feedback stage adjusting output currentof the amplifier circuit based on the relative voltage levels of thefirst and second integrator outputs.
 35. The computer system of claim 28wherein the integrator circuit of the sensing circuit is a firstintegrator circuit, and the sensing circuit further comprises a secondintegrator circuit having a pair of integrator input nodes and a pair ofintegrator output nodes, the second integrator circuit electricallyinterposed between the first and second integrator outputs of the firstintegrator circuit and the comparator, each integrator input node of thepair electrically coupled to a respective integrator output of the firstintegrator circuit and each integrator output node of the pairelectrically coupled to a respective input node of the comparator.
 36. Amethod of sensing a data state of a memory cell, comprising: couplinginput and output terminals of an integrator circuit according to a firstconfiguration for a first portion of a first time period; coupling theinput and output terminals of the integrator circuit according to asecond configuration for a second portion of the first time period; thesecond configuration changing polarity of the integrator circuit fromthe first configuration; based on voltage levels at the output terminalsof the integrator circuit, generating a clocked output signalrepresentative of a value; and averaging the value of the clocked outputsignal over a second time period.
 37. The method of claim 36, furthercomprising amplifying the voltage levels at the output terminals of theintegrator circuit prior to generating a clocked output signal.
 38. Themethod of claim 36 wherein the first portion and the second portion ofthe first time period are equal.
 39. The method of claim 36, furthercomprising: providing a first current having a first polarity to a firstof the output terminals of the integrator circuit and providing a secondcurrent having a second polarity opposite the first polarity to a secondof the output terminals of the integrator circuit; and switching theprovision of the first and second currents to the first and secondoutput terminals of the integrator circuit based on the value of theclocked output signal.
 40. The method of claim 36 wherein the secondtime period is greater than and a multiple of the first time period. 41.A method of sensing a data state of a memory cell, comprising:periodically switching coupling of input terminals and output terminalsof an integrator circuit from a first configuration to a secondconfiguration, the second configuration changing polarity of theintegrator circuit from the first configuration; periodically comparingoutput signals provided by the integrator circuit; based on thecomparison, generating an output signal having a voltage representativeof a value; and averaging the value of the output signal over a timeperiod.
 42. The method of claim 41, further comprising amplifying theoutput signals provided by the integrator signal prior to the periodiccomparison.
 43. The method of claim 41, further comprising: providing afirst current having a first polarity to a first of the output terminalsof the integrator circuit and providing a second current having a secondpolarity opposite the first polarity to a second of the output terminalsof the integrator circuit; and switching the provision of the first andsecond currents to the first and second output terminals of theintegrator circuit based on the value of the output signal.
 44. Themethod of claim 41 wherein the switching occurs at a period greater thanat which the comparing occurs.
 45. The method of claim 44 wherein theperiod of the switching is a multiple of that at which the comparingoccurs.